JBITS XHWIF Interface #2:  for the XSV-100 Board. (Electronic Schematic / circuit added 4/02)

JBITS XHWIF Interface:  for the XS40-005XL Board. (Electronic Schematic / circuit added 4/02)

Loadable LED Register:  showing the interaction between the microcontroller and the CPLD or FPGA on the XS Board. (Electronic Schematic / circuit added 4/02)

Look Ahead Approach Tames Large FPGA Counters:  12/22/94 EDN Design Ideas /  (added 2/06) 

Measuring Jitter in Digital Systems (AN 1448-1):  Agilent Application Note   (app note added 6/06)

Modulator's Design Cuts FPGA's Gate Count:  01/06/94 EDN-Design Ideas / (Circuit / schematic design added 6/06) The pulse-width modulator (PWM) macro in Fig 1 requires only half as much logic as a conventional 2-counter design. With the help of extra logic, a synchronous, loadable up/down counter can encode information in the duty cycle of a constant-frequency, constant-amplitude signal....

PC to SRAM Interface:  for the XSV Board (Univ. of Queensland) (Electronic Schematic / circuit added 4/02)

PC/XS Transfer:  A circuit and C code for bidirectional transfer of data between an XS40 Board and a PC. (Electronic Schematic / circuit added 4/02)

Plastic Pin Grid Array (PPGA):  National Semiconductor - Application Note   (app note added 2/06)

PLL Implements FPGA Based SDRAM Controller :  05/21/98 EDN-Design Ideas / (added 2/06)  As FPGA capabilities increase and time to market decreases, FPGAs gain more acceptance for implementing both data and control paths. Thus, they find wide use as controllers and datapath glue logic for fast-page DRAMs. Synchronous DRAMs (SDRAMs), whose control signals use a clock input as reference, are a natural target for FPGA-based controllers. SDRAMs operate at frequencies of 100 MHz and higher (in contrast with fast-page DRAMs, for which a 60-MHz memory-system clock was considered high). Figure 1 shows a way to implement FPGA-based SDRAM controllers. Figure 2 shows the timing for a Xilinx XC4010E-2 device. You can apply the method to FPGAs from other vendors, as well as to high-frequency systems other than SDRAMs.... 

Priority Encoders Slip into FPGAs:  02/17/94 EDN Design Ideas / (added 2/06)

PS/2 Interface:  for the XSV Board (Univ. of Queensland) (Electronic Schematic / circuit added 4/02)