Reconfigurable Coprocessor for Redundant Radix4 Arithmetic:  project implements four arithmetic and four logic operations using a fast parallel multiplication scheme. The coprocessor is hosted in an XS40 Board that interfaces to a PC through the parallel port. (Electronic Schematic / circuit added 4/02)

RISC µP Implements Fast FIR Filter:  01/21/99 EDN-Design Ideas / (added 11/05)  When it comes to implementing a fast FIR filter, current RISC µPs can compete with DSP µPs. The FIR algorithm continuously implements the following equation:  N=n–1    Out=Sum[in(t[-]n)coeff(n)]  N=0,....

RISC µP Supports IEEE Parallel Port Standard:  01/18/96 EDN-Design Ideas / (added 11/05) 

Sampling of Signals for Digital Filtering and Gated Measurements:  DN2 -  Design Notes (Linear Technology) (app note added 1/06)

SDRAM Controller Module:  for the XSA-50 and XSA-100 Board that makes the SDRAM look like a simple static RAM. (Electronic Schematic / circuit added 4/02)

SDRAM Interface Slashes Pin Count:  02/05/2004  EDN-Design Ideas  In low-noise analog circuits, a high-gain amplifier serves at the input to increase the SNR. The input signal level determines the input-stage gain; low-level signals require the highest gain. It is also standard practice in low-noise analog-signal processing to make the circuit's bandwidth as narrow as possible to pass only the useful input-signal spectrum. (added 10/05)

Simple Circuit Provides Power Sequencing:  10/14/04 EDN Design Ideas  / (added 10/05)  ASICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their start-up sequencing. Often, I/O voltages, which usually have the highest voltage, must come up first, followed by all other voltage rails in a high-to-low order, with the core voltage last. This scenario may also require that one supply rail not exceed another by more than a diode drop; otherwise, excessive c...

Simple FIFO Provides Data Width Conversion:  09/26/02 EDN Design Ideas  / (added 1-/05)  Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1).

Simplified Programming of Altera FPGA's using a SCANSTA111/112 Scan Chain Mux:  National Semiconductor - Application Note   (app note added 2/06)

Speed FPGA Debug with Mixed-Signal Oscilloscopes:  Agilent Application Note   (app note added 6/06)

SRAM Interface:  for the XSV Board (Univ. of Queensland) (Electronic Schematic / circuit added 4/02)

Stereo Loopback Circuit:  that accepts a digitized stereo signal from the ADC of the XStend Board codec and loops the signal back to the codec DAC stage for output as a stereo signal. (Electronic Schematic / circuit added 4/02)

USB Macro:  that combines a complete USB transaction layer with an 8051 microcontroller core and a functional block that implements the application-specific functions. This macro was developed and is supported by Trenz Electronics for use with an XSV Board. (Electronic Schematic / circuit added 4/02)

Using an SZ Volt Board Xchecker Interface:  Zess Corporation / Application Notes / configures the CPLD on the XSV Board so the By checker interface is enabled. (app note added 4/02)

Using the 16700 Logic Analyzer with the Xilinx ChipScope ILA:  Agilent Application Note   (app note added 6/06)