AC power measurement uses PWM & PAM -  EDN-Design Ideas 06/17/2015    Use clever pulse modulation techniques to multiply signals and measure power.   __ Circuit Design by Adolfo Mondragon

Clock multiplier circumvents PLL -  05/13/99 EDN-Design Ideas Using a standard PLL circuit, such as the CMOS 4046B with some passive components, is a well known way to design a clock multiplier.   __ Circuit Design by Jose Carlos Cossio, Santander, Spain

Cockcroft Walton Diode Voltage Multipliers -  These circuits generate high voltages and can cause dangerous shocks! Do not build these devices unless you are experienced and qualified to work on high voltage devices. __ Contact: Charles Wenzel of Wenzel Associates, Inc.

Frequency multiplier improves line readings -  EDN-Design Ideas March 26, 1998    [ NOTE : File has multiple design, scroll for this one.]  Because of the low frequencies involved, accurately measuring line-frequency variations is complicated. When you use an ordinary frequency counter with a 1-sec gate time, the reading would be 59, 60, or 61 Hz. To obtain 0.01-Hz accuracy, you must increase the gate time to 100 sec, a scale that most frequency counters do not offer.__ Circuit Design by Yongping Xia, Teldata Inc, Los Angeles, CA

Frequency Tripler Using the CA3028 -  Here is a simple frequency tripler using a CA3028 differential amplifier.  The CA3028 has internal bias resistors for setting the differential amplifier's current at about 7 mA when connected as shown.  With this current, the output level is about 0 dBm at 30 MHz with a 1v p-p, 10 MHz input.   __ Contact: Charles Wenzel of Wenzel Associates, Inc.

Gyrator -  The gyrator principle uses the effect that the value of input capacitance at the base of a transistor is effectively multiplied by the current gain of the transistor.   __ Designed by Andy Collison

HCMOS Gates Make Frequency Multipliers -  The rapid edges produced by HCMOS logic ICs are rich in harmonics which can be selectively tuned to make simple frequency multipliers.  The desired harmonic may be selected in a number of ways but a few points should be observed.  First, the tuning network should not present an excessive capacitive
load to the output of the IC and it is recommended that a series current limiting resistor __ Contact: Charles Wenzel of Wenzel Associates, Inc.

Odd-order Diode Multiplier -  The purpose of the circuit is to take advantage of the superior noise and switching characteristics of Schottky barrier diodes to make a high performance odd-order frequency multiplier.  Modern quartz oscillators have reached a level of performance where it has become difficult to multiply the fundamental frequency without degrading the phase noise by more than the unavoidable 20 dB per decade of multiplication.  Thanks to the Schottky barrier diode's extremely low flicker noise, this circuit adds little excess noise __   Reprint courtesy of RF Design Magazine

Q Multiplier -  A few weeks ago I posted to QRP@WW the modifications to convert a cheap radio to the HF amateur bands.  I have dug-out one of my radio's that was modified for 7MHz and found yet another circuit was built into it.  This is the circuit for a Q-multiplier to reduce the IF bandwidth.  I do not have any idea where this circuit came from, but other than scribbled on the back of a cigarette packet some 20 years ago. __ Designed by Harry Lythall-SM0VPO

Q-multiplier -  This is the circuit for a Q-multiplier to reduce the IF bandwidth.  I do not have any idea where this circuit came from, but it is NOT originally mine, so I claim NO credit.  The circuit is basically an oscillator that does not quite oscillate, so when it is connectd to the IF HOT end of the first IF transformer it will increase the Q-factor, thereby reducing the IF bandwidth considerably.  It does this by cancelling the losses in the 1st IF transformer using gain from an additional transistor circuit.   __ Designed by Harry Lythall-SM0VPO

Two Diode Odd-Order Multiplier -  It is often necessary to multiply the frequency of low noise oscillators without significantly degrading the phase noise beyond the theoretical 20 log (N).  Low noise frequency doublers constructed with Schottky signal diodes are readily available but higher-order multipliers often __ Contact: Charles Wenzel of Wenzel Associates, Inc.

750 MHz Power Doubler & Push-Pull CATV Hybird Modules using Gallium Arsenide 3/21/96  -  App Note  Doc #920  ___ California Eastern Laboratories

Delay Line implements Clock Doubler -  Timing delays are undesirable in most digital circuits.  However, in some cases, delays can be useful—to deal with a µP-speed-compatibility issue, for example.  The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler.  Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock.  Using a more precise delay line, the circuit can output a triple clock (Figure 1b).  __ Circuit Design by Y Li, SAE magnetics  HK Ltd, Guang Dong Province, China  7/18/96

Diode Frequency Doublers -  Ordinary fast switching silicon diodes, special fast recovery junction diodes, schottky barrier diodes, varactors and even old-fashioned germanium diodes or vacuum tubes may be used to construct signal powered frequency doublers __ Contact: Charles Wenzel of Wenzel Associates, Inc.

Introduction, Definition of terms, Q&Asdoub9-2 -  Application Note___ MiniCircuits.com

Frequency Multiplier Circuits