74ACT74 Makes Low-Skew Clock Divider:  12/17/98 EDN-Design Ideas  / (added 6/06)  Serial-data systems often generate an internal clock at twice  data rate for mid-bit sampling or for generating bi-phase codes. External equipment and some internal processes require a clock that runs at  data rate. Simply dividing  twice-rate clock with a flip-flop generates a data-rate clock that is skewed by one logic delay with respect to  input. This delay can be a significant fraction of  bit period. You can use specialized PLL-based low-skew divider chips to deal with this problem, but se chips have a limited frequency range and are not designed to follow rapid changes in  data rate.... 

Amplifiers Perform Precision Divide by 2 Circuit:  02/06/03 EDN Design Ideas  /  (added 1/05)  The classic implementation of a voltage-halving circuit uses two equal-value resistors. Using 1% resistors provides a divider output with 2% accuracy. For most applications, this performance is cost-effective and more than adequate. However, when you need extreme precision, this approach requires correspondingly accurate resistors and can become expensive....

Blacet Frequency Divider:  (circuit added 10/06)

Charge Pump Circuit Divides by Two:  02/18/99 EDN-Design Ideas / (added 6/06) Small size and efficiency approaching 100% make switched-capacitor charge pumps popular for voltage doubling and inverting in miniature dc-dc applications. Few are aware, however, that most charge pumps can halve as well as double or invert an input voltage. The increasing adoption of low-voltage logic makes this ÷2 capability useful for generating low-voltage supplies in portable equipment. You can use it, for example, to convert a 3.6V RF-supply voltage to 1.8V for powering low-voltage logic (Figure 1). Simply reversing  input and output of a voltage doubler makes it a voltage divider. Implementing this scheme with MAX660 or MAX1683 voltage-doubler charge....

Cheap 40kHz Clock:  (circuit / schematic design added 6/06)

Circuit Conditions Variable Duty Cycle Clock:  02/17/97 EDN-Design Ideas / (added 6/06) The circuit accepts an input clock of any duty cycle and generates any desired duty cycle at the output. You need to add only one flip-flop to the earlier design to generate an arbitrary-duty-cycle output. You can use the circuit to correct a non-50% input to a 50% output or to create a non-50% output from any arbitrary input duty cycle. The input-clock signal serves as the clock signal to a D flip-flop, which is configured as a toggle flip-flop. The flip-flop's output signal is thus a 50%-duty-cycle, half-frequency version of the input clock, independent of the input-clock duty cycle. The flip-flop's output passes through the clock-doubler circuit (from the earlier Design Idea, Figure 1b). The doubler circuit (delay element t and XOR gate) doubles the frequency. The doubling restores the output signal to the same frequency as the input (Figure 1a)....

Circuit divides frequency by N+1:  07/11/02 EDN Design Ideas  /  (added 1/05)  Digital frequency dividers usually use flip-flop stages that connect the Q pin to the D data-input pin of the following stage. This configuration creates a binary waveform that you can feed back to the input. You can divide any integer lower than 2N with minimal stages, where N is the number of stages....

Clock Divider Circuit:  (circuit / schematic design added 6/06)

Counter Provides Divide by 45 Function:  05/22/97 EDN-Design Ideas / (added 3/03)  

Frequency Divider Adapts to I/O Conditions:  12/05/96 EDN-Design Ideas / (added 11/05) CanadaThe circuit in Figure 1 accepts an input clock signal, such as from a crystal oscillator, and divides the frequency according to the input divisor word. You can easily modify the basic design of this versatile PLD-based divider to handle different I/O conditions. The design uses the FLEX8000 family of PLDs from Altera Corp (San Jose, CA). The core of the design generates the appropriate edges to toggle the output T flip-flop to create a clock signal with a duty cycle of approximately 50%. The input divisor word serves as the reference for the 8COUNT countdown counter. This counter counts down from the divisor word and raises the COUT flag when the count reaches zero. The complement of COUT synchronously resets the reference value of the counter to restart the process....

Frequency Doubler Operates on Triangle Waves:  12/05/96 EDN-Design Ideas / (added 3/03)

Precision Divide by Two Analog Attenuator Needs No External Components:  03/17/05 EDN Design Ideas  / (added 11/05)  Many modern A/D converters offer only a 5V input range, and using these converters with a 65V or larger input signal gives the designer a problem: how to discard half of a good analog signal without introducing errors and distortion. To solve the problem, you can use an attenuator comprising two operational amplifiers and two resistors (Figure 1).

Synthesize Optimal Digital-Frequency Dividers:  05/13/99 EDN-Design Ideas / (added 11/05)

Unusual Frequency Dividers:  (electronic circuit added 7/03)