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Dual-Input Sample-And-Hold Amplifier Uses No External Resistors - 14-Dec-07 EDN Design Ideas: A sample-and-hold amplifier sums two inputs and holds that sum when triggered Design by Marián Štofka, Slovak University of Technology, Bratislava, Slovakia Dual Slope-Sampling Solar Engine - if you had time to experiment with the ALF type SE circuit you may have discovered some of its shortcomings with regard to a Power Smart Head adaptation. The problem is that HCMOS
gates are power hungry when used as SE voltage comparators when the analog input voltage is near the CMOS
switching threshold. if an HCMOS
gate is used without sampling, the chip supply current can be as high as 70mA with the comparator input voltage near the trigger threshold (Vcc / 2). __ Designed by Wilf Rigter
Gain-of-three Amplifier requires no external resistors - 17-Aug-06 EDN Design Ideas: One IC provide as wideband amplification and minimizes parts count Design by Marián Stofka, Slovak University of Technology, Bratislava, Slovakia
Gain-of-two sample-and-hold Amplifier uses no external resistors - 11/08/07 EDN Design Ideas: TWhen you need to simultaneously sample a signal and amplify the signal level, you can cascade a common gain-of-one sample-and-hold amplifier and an amplifier with a voltage gain of one. With some exceptions, such an amplifier has two external resistors (Reference 1). These resistors dissipate power even at the steady state of the sample-and-hold amplifier. in monolithic IC s, power dissipation and the consequent generation of heat from resistors are not the only items in the list of the drawbacks of external resistors. Design by Marián Štofka, Slovak University of Technology, Bratislava, Slovakia
Improve On Temperature Measurement - 05/02/02 EDN Design Ideas: When current pulses with a stable iHiGH/iLOW ratio modulate a semiconductor junction, the ensuing voltage difference (for example, ΔVBE for a bipolar transistor] is a linear function of the absolute (Kelvin] temperature, T. You can us Design by Alexander Bell, Infosoft International Inc, Rego Park, NY
Increase the range of memorized voltage for a sample-and-hold Device - 22-Jan-09 EDN Design Ideas: Using MOSFETs and bipolar transistors, you can increase the sample-and-hold voltages to as much as ±25V Design by Yakov Velikson, Lexington, MA
Infinite-Hold Zeros Out Long-Term Drift - 03/03/94 EDN Design Ideas: The infinite-hold circuit in Fig 1 automatically zeros out long-term drift from an instrument or a sensor. in operation, a control system (not shown]periodically takes the instrument or sensor off line and applies a known stimulus. The known stimulus generates a baseline-output signal Design by William R Penrose and Li Pan, Transducer Research, Naperville, IL
Inverting sample-and-hold Amplifier requires no external resistors - 08/02/07 EDN Design Ideas: Eliminating external feedback resistors in an inverting sample-and-hold amplifier allows it to exploit the full bandwidth of its op amps Design by Marián Štofka, Slovak University of Technology, Bratislava, Slovakia
Level-Shifts AC Signals - 10-Jul-03 EDN Design Ideas: AC signals can emanate from many sources, and many of these sources are incompatible with the most popular interface voltages, such as TTL. A temptation always exists to capacitively couple the ac signals because capacitive couplin Design by Ron Mancini, Texas Instruments, Bushnell, FL
NCO technique helps µC produce clean analog signals - EDN-Design ideas – April 15, 1999 [ NOTE: FILE
has multiple design, scroll for this one.] A recent Design idea described a method for producing an analog voltage from one digital output of a µC ("Generate an analog signal with a µC, " EDN, Oct 22, 1998, pg 108). The method involves generating a PWM output with a controlled duty cycle and filtering the switching waveform with a simple single-pole RC filter. Although this method provide as an accurate dc output with 8 bits of resolution, it requires a filter with a low cutoff frequency to reduce the ripple to less than 1 LSB. Design by Steve Ploss, Veridian Corp, Wright Patterson AFB, OH
Precision Sample & Hold Amplifier - CMOS
amplifiers are very good for use in Sample-and-Hold circuits because the pA's of bias current does not drain off charge held on the hold capacitor. A dual amplifier can be used to buffer the input signal and also the hold capacitor. The slew rate of the circuit is limited by the output current limit of the input amplifier charging the 0.1uF hold capacitor__ Linear Technology/Analog Devices App Note, Mar 16, 2010
Precision T/H Amplifier Uses 3.3V Supply - 06/22/95 EDN Design Ideas: The track-and-hold (T/H] circuit in Fig 1 works well in applications using a low-voltage single supply, such as in battery-powered designs. Despite the low supply voltage, output-signal dynamic range remains high thanks to the rail-to-rail output swing of the amplifiers and switches. S/N ratio is also high because Design by John McDonald, Analog Devices, Santa Clara, CA
Resistance Measurement using Sample & Hold Method - A sample and hold circuit, as the name implies, samples an analogue input signal and holds its value until the input is again sampled.Fig.1 shows the basic principle of the...__ Electronics Projects for You
RF transmitter uses AM I encoding - 11/24/99 EDN Design Ideas: Although alternate-mark-inversion (AMi]encoding is well-suited for direct-conversion FM transmission, designers often overlook the technique. AMi, a three-phase, synchronous-encoding technique, uses bipolar pulses to represent logic ones and no signal to Design by Paul Sofianos
S/H minimizes aperture - EDN-Design ideas – April 15, 1999 [ NOTE: FILE
has multiple design, scroll for this one.] Conventional sample-and-hold (S/H) circuits use one hold capacitor that charges during the track phase and disconnects during the hold phase. The voltage that the capacitor holds usually drives an A/D converter that operates synchronously with the S/H control signal. This approach can sometimes place excessive demands on the S/H circuit's bandwidth and settling capabilities. You can improve performance by using two hold capacitors to implement continuous sampling (Figure 1). One capacitor or the other is always sampling the input signal, and the output is always the held value. A phase-reversal switch (IC 1) interconnects the input, output, and hold capacitors. Design by John Guy, Maxim Integrated Products, Sunnyvale, CA
Sampling peak Detector has shutdown feature - 05/16/02 EDN Design Ideas: You face a serious problem in using a slow ADC with a fast peak detector. The circuit in Figure 1 allows a slow ADC to measure a fast, sampled signal peak. The 100-MHz peak detector for ultrasonic-pulse sampling uses a fast MAX4231 amplifier from Maxim (www.maxim-ic.com]. This amplifier has a shutdown feature that facilitates power savings without losing the sampled information Design by Shyam Tiwari, Sensors Technology Private Ltd, Gwalior, India
Test Sample-And-Hold Amplifiers - 4-Mar-10 EDN Design Ideas: Measure voltage drop with a digital voltmeter Design by Marián Štofka, Slovak University of Technology, Bratislava, Slovakia
Video Design Idea: Diagnose setup & hold times in synchronous & asynchronouss - 18-Oct-07 EDN Design Ideas: Metastability of digital circuits can become a problem if you don't properly account for setup and hold times in synchronous circuits, or at random in the case of asynchronous inputs Design by Staff |
