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Delay Circuits
Delay Circuits:  #'s - Q     R - Z

 

Last Updated: December 25, 2017 01:50 PM

Circuits Designed by Dave Johnson, P.E.

Long Period Computer Watch Dog Timer This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a computer.  Should the computer fail to send a pulse, the output changes state.  The time can easily be set from seconds to hours. . . Circuit by David Johnson P.E.-January, 1998

On/Off Latch Circuit with 2 Second DelayA Discover Circuits visitor needed a latch circuit which could operate using a power supply voltage ranging from 3v to 24v.  He wanted to use a tiny pushbutton switch to turn on and off power to a load.  However, he wanted a 2 second delay between the switch activation and the state change of the output. . . Circuit by Dave Johnson P.E.-June, 2013

Press & Hold Latching CircuitA Discover Circuits visitor needed a latch circuit which could operate using a power supply voltage ranging from 3v to 24v.  He wanted to use a tiny pushbutton switch to turn on and off power to a load.  However, he wanted a 2 second delay between the switch activation and the state change of the output . . . Hobby Circuit designed by David Johnson P.E.-June, 2013


Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

12 sec to 90 Minute Time Relay -  Schematic and notes only, no circuit description provided.   __ Designed by Tony van Roon  VA3AVR

Butterworth filter has adjustable group Delay -  08/08/02  EDN-Design Ideas The Sallen-Key realization of a 5.25-MHz, three-pole Butterworth filter has a gain of 2V/V and can drive 75Ω back-terminated coax with an overall gain of 1   (Figure 1).  Used to reconstruct component-video   (Y, Pb, Pr] and RGB signals, t__ Circuit Design by William Stutz, Maxim Integrated Products, Sunnyvale, CA

Computer, Long Period, Watch Dog Timer -  This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a computer.  Should the computer fail to send a pulse, the output changes state.  The time can easily be set from seconds to hours . . . Hobby Circuit designed by Dave Johnson P.E.-January, 1998

Delay Line Aids in One-shot Simulations -  EDN-Design Ideas 04/26/01     Many designers use small pulse generators to delay signals, open timing windows, drive sample/hold circuits, and other functions.  Though the hardware implementation of these generators does not pose any problems, the lack of dedicated circuitry sometimes puzzles the Spice simulation of the system.  __ Circuit Design by Christophe Basso, On Semiconductor, Toulouse, France

Delay line eases Spice Dead-time generation -  03/02/00  EDN-Design Ideas Generating complementary clock signals in a Spice simulation is an easy task.  However, this task gets much harder if you need to introduce some dead time into the signals.  This difficulty is especially true when you're dealing with a variable-pulse-width-__ Circuit Design by Christophe Basso, On Semiconductor, Toulouse, Cedex, France

Delay line has wide duty-cycle range -  06/27/02 EDN-Design Ideas Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%.  A limited range of available delays(2 to 100 nsec per tap] further limits their use.  Longer delay is available with one-shot multivibrators of standard digital-logic families, but those devices do not retain duty-c__ Circuit Design by John Guy, Maxim Integrated Products, Sunnyvale, CA

Delay Line implements Clock Doubler -  Timing delays are undesirable in most digital circuits.  However, in some cases, delays can be useful—to deal with a µP-speed-compatibility issue, for example.  The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler.  Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock.  Using a more precise delay line, the circuit can output a triple clock (Figure 1b).  __ Circuit Design by Y Li, SAE magnetics  HK Ltd, Guang Dong Province, China7/18/96

Delay line upgrades vintage scope -  04/18/02 EDN-Design Ideas Vintage triggered-sweep oscilloscopes find use in many applications.  However, they have no internal delay line, so they can't display the pulse that triggers the sweep.  Moreover, early laboratory scopes contain delay lines having insufficient delay to display such pulses during a uniform portion of the sweep__ Circuit Design by Robert Houtman, Blaine, WA

Delay Simulator Debugs Communications Equipment -  10/27/94 EDN-Design Ideas  Phone calls over satellite circuits experience a Ľ-sec transmission delay in each direction.  The low-cost circuit(around $20]in Fig 1a simulates this delay and provIdeas hooks for inserting noise, echo, and other__ Circuit Design by Stan Sasaki, Lake Oswego, OR

Delayed Audible Alarm -  In this circuit, three multivibrator-type oscillators and a ripple counter are configured to produce an interesting, alarming sound, using two inexpensive integrated circuits plus a few other components.  Operation is as follows:U1A and U1B and their associated components are configured as multivibrators, each of a selected audio frequency __ Designed by Arthur Harrison

Delayed Power using an SCR This circuit Creates a Tiny Power Delay to a Circuit.  Read Why I designed it.   __ Designed by G.L. Chemelec

Delayed Turn-On Relay -  This circuit is a delayed turn-on relay driver and can produce time delays for up to several minutes with reasonable accuracy.  The 14001 (or 4001) CMOS gate here is configured as a simple digital inverter.  Its output is fed to the base of a regular 2N3906 (PNP) transistor, Q1, at the junction.   __ Designed by Tony van Roon  VA3AVR

Dome light dimmer (with Delay) -  For all you guys out there that want a fading dome light (aka courtesy light aka theatre lighting) without having to pay for one, you can build your own.  I have attached the schematics and you can build it for a few bucks given that you don't have any spare components lying around otherwise it can cost you absolutely nothing.  Of course you can rip some parts from your TV, CD player, radio, etc.  , but I'm not responsible for the damage you cause this way [b:e43bc460fa]The way it works[/b:e43bc460fa] I won't bother you with technical __

Feedback Eliminates CCD-Driver Delay Mismatch -  18-Sep-03 EDN-Design Ideas In a CCD(charge-coupled device], packets of charges shift across the array.  The transistor array, also called a bucket-brigade shift register, receives drive from a dual-phase clock signal.  Dual-phase clock signals comprise two synchronized clock signals that are 180° out of phase.  High peak-output-current CCD drivers can buffer the logic-level clock signals and turn them into high-voltag__ Circuit Design by Mike Wong, Intersil-Elantec, Milpitas, CA

Generating a Delayed Pulse with a dual 555 Timer -  The circuit below illustrates generating a single positive pulse which is delayed relative to the trigger input time.  The circuit is similar to the one above but employs two stages so that both the pulse width and delay can be controlled.  When the button is depressed, the output of the first (__ Designed by Bill Bowden

Generating Long Time Delays -  Generating long delays of several hours can be accomplished by using a low frequency oscillator and a binary counter as shown below.  A single Schmitt Trigger inverter stage (1/6 of 74HC14) is used as a squarewave oscillator to produce a low frequency of about 0.5 Hertz.  The 10K resistor in series with the input (pin 1) reduces the capacitor discharge current through __ Designed by Bill Bowden

Group Delay Equalizer has Gain More than One -  10/12/95 EDN-Design Ideas For numerous applications, flat group delay (linear phase) is necessary to maintain system performance.  The common group-delay equalizer of Fig 1a has unity gain and is a popular way to equalize data filters or alias filters when phase compensation is necessary.  The alternative equalizer of Fig 1b, however, can provide a gain greater than one for systems that require additional gain (and when providing that gain elsewhere is impossible or impractical).   __ Circuit Design by Mark Weigel, Scottsdale, AZ

High & Low Voltage Cut Off with Time Delay -  The power line fluctuations and cut-offs cause damages to electrical appliances connected to the line.  It is more serious in the case of domestic appliances like fridge and air conditioners.  If a fridge is operated on low voltage, excessive current flows through the motor, which heats up, and get damaged __ Contact: IQ Technologies

Long Period Computer Watch Dog Timer -  This circuit uses a simple 4060 IC oscillator/timer that is reset periodically by a computer.  Should the computer fail to send a pulse, the output changes state.  The time can easily be set from seconds to hours. . . Circuit by David Johnson P.E.-January, 1998

Low Voltage , High Current Time Delay -  In this circuit a LM339 quad voltage comparator is used to generate a time delay and control a high current output at low voltage.  Approximatey 5 amps of current can be obtained using a couple fresh alkaline D batteries.  Three of the comparators are wired in parallel to drive a medium power PNP transistor (2N2905 or similar) which in turn drives a high current NPN transistor (TIP35 or similar).  The 4th comparator is used to generate a time delay after the normally closed switch is opened __ Designed by Bill Bowden

On/Off Latch Circuit with 2 Second Delay -  A Discover Circuits visitor needed a latch circuit which could operate using a power supply voltage ranging from 3v to 24v.  He wanted to use a tiny pushbutton switch to turn on and off power to a load.  However, he wanted a 2 second delay between the switch activation and the state change of the output. . . Circuit by Dave Johnson P.E.-June, 2013

Power-Off Time Delay Relay -  The two circuits below illustrate opening a relay contact a short time after the ignition or ligh switch is turned off.  The capacitor is charged and the relay is closed when the voltage at the diode anode rises to +12 volts.  The circuit on the left is a common collector or emitter follower and has the advantage of one less part since a resistor is not needed in series with the transistor base.  However the voltage across the relay coil will be two diode drops less than the supply voltage, or about 11 volts for a 12.5 volt input. __ Designed by Bill Bowden

Power-on sequencing using TL431 in comparator Mode -  TL431 as a comparator.  Delay timers.  Power-on sequencers.  TL431 without feedback can be considered as an NPN or N-MOS device with high transconductance and precise 2.5V turn-on voltage.  Tube heads beware: the upper (+supply) pin on TL431 is cathode, lower (-supply) , anodeit's another world.   __ Contact: klausmobile @ yahoo.Com

Power-On Time Delay Relay -  Here's a power-on time delay relay circuit that takes advantage of the emitter/base breakdown voltage of an ordinary bi-polar transistor.  The reverse connected emitter/base junction of a 2N3904 transistor is used as an 8 volt zener diode which creates a higher turn-on voltage for the Darlington connected transistor pair.  Most any bi-polar transistor may be used, but the zener voltage will vary from about 6 to 9 volts depending on the particular transistor used.  Time delay is roughly 7 seconds using a 47K resistor and 100uF capacitor and can be reduced by reducing the R or C values. __ Designed by Bill Bowden

Press & Hold Latching Circuit -  A Discover Circuits visitor needed a latch circuit which could operate using a power supply voltage ranging from 3v to 24v.  He wanted to use a tiny pushbutton switch to turn on and off power to a load.  However, he wanted a 2 second delay between the switch activation and the state change of the output . . . Hobby Circuit designed by David Johnson P.E.-June, 2013

PTT Delay Circuit -  The delay circuit is inserted between the controller and transmitter to provide a set-able time delay keeping the transmitter keyed when using "zero hang time" and linking to another machine. To use this circuit, the controller's repeater ptt must be configured "high true" (dip switch 2 on) . __ Designed by Kevin Custer  W3KKC


Delay Circuits:  #'s - Q     R - Z


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