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Gated clock has duty-cycle control: 08/17/00 EDN-Design Ideas / (added 2/06) The circuit in Figure 1 produces
clock pulses with variable duty cycle from a gated clock. The output of the circuit, pulse, is always 180° out of phase with the clock input. When the delay-logic elements, IC5 and IC7, have
the same propagation delays, the duty cycle of the circuit's output is 50%. The circuit produces gated clock pulses when the gate input, gate, is high and the active-low reset, reset_n, is
high. Increasing the propagation delays of the increase-duty-cycle delay-logic element, IC5, causes an increase in the duty cycle of the gated-clock output, pulse. The decrease-duty-cycle
delay-logic element, IC7, reduces the duty cycle of the gated-clock output. Listing 1 is a Verilog model of the circuit; |
