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DC Power Wire also Carries Clock or Data - 03/13/98 EDN-Design Ideas:
-High-side current-sense amplifier, IC1, offers a simple method of combining low-speed
clocks or other signals with dc power in cables between subsystems.....(design idea
added 6/06) |
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DDR2: The Next Generation Main Memory - Pericom Semiconductor App Note # 07)8 (app
note added 02/05) |
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Delay Line has Wide Duty Cycle Range - 06/27/02 EDN-Design Ideas: Today's digital
delay lines can process pulses no shorter than their delay times, and that restriction
confines the devices to applications in which the duty cycle remains near 50%. A
limited range of available delays (2 to 100 nsec per tap)further limits their use.
Longer delay is available with one-shot multivibrators of standard digital-logic
families,.....(design idea added 1/05) |
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Delay Line implements Clock Doubler - 07/18/96 EDN-Design Ideas: (design idea
added 3/03) |
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Designing for Minimal Jitter When using Clock Buffers - Pericom Semiconductor
Application Note # 024 (app note added 02/05) |
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Differences of Pericom Superclocks & Competitor Programmable Skew Clocks - Pericom
Semiconductor Application Note # 061 (app note added 02/05) |
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Digital Clock with Timer & Solar Panel Regulator - This is a combination digital
clock timer and solar panel charge controller used to maintain a deep cycle battery
from a solar panel. The timer output is used to control a 12 volt load for a 32....
(added 2/07) |
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Direct Digital Synthesizers in Clocking Applications Time Jitter in Direct Digital
Synthesizer-Based Clocking Systems - AN-823 Analog Devices Application Notes
(app note added 2/06) |
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Don't let Slow circuits Slow down the system - 08/17/98 EDN-Design Ideas: (design
idea added 2/06) |
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Dynamic Clock Provides for Zero Wait States - 03/27/97 EDN-Design Ideas: (design
idea added 3/03) |
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Emi Reduction Techniques - Pericom Semiconductor App Note # 011 (app note added
02/05) |
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Fail-Safe Monitoring & Clock Frequency Switching using the PIC16f684 - Microchip
Application Note Published 16-Dec-03 (app note added 2/06) |
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Frequently Asked Questions on DDR Applications - Pericom Semiconductor Application
Note # 027 (app note added 02/05) |
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Garden Timer with Remote control - Few years ago we control the lights in the
garden with a automatic-timer-switch, very nice but when the evening gets longer or
shorter we had to adapt the timer each week. In that time I came in contact with
programming microprocessors so my first project was born. The first garden timer was a
simple 1 output. The timing was controlled by the PIC and every month I had to change
the minutes. So back to the table and design the second garden timer able to control 3
relays, left, mid and right side of the garden. It provided also 4 modes: – always off
– always on – from dusk to dawn – from dusk to timer and the timing was dedicated to a
RTC DS1307. ….(design added 11/08) |
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Gated Clock has Duty Cycle Control - 08/17/00 EDN-Design Ideas: The circuit in
Figure 1 produces clock pulses with variable duty cycle from a gated clock. The output
of the circuit, pulse, is always 180° out of phase with the clock input. When the
delay-logic elements, IC5 and IC7, have the same propagation delays, the duty cycle of
the circuit's output is 50%. The circuit.....(design idea added 1/06) |
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General Routing Techniques with Emphasis on PI6c10x Clocks - Pericom Semiconductor
App Note # 008 (app note added 02/05) |
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Generating Multiple Clock Outputs from the AD9540 - AN-769 Analog Devices
Application Notes (app note added 2/06) |
