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Gate Array Circuits
Gate Arrays:  #'s - E       F - Q        R - Z

Last Updated: October 13, 2017 03:04 AM


Links to electronic circuits, electronic schematics, designs for engineers, hobbyists, students & inventors:

2 Gates Expand ASIC's Memory Decoding Range -  03/29/01 EDN-Design Ideas Many electronic circuits implement chip-select lines on an ASIC.  From  beginning of  design cycle,  chip selects, CS0 to CS4, have defined bases on  memory map  (Figure 1).  Adding functions__ Circuit Design by Vinh Hoang, Ericsson Inc, Brea, CA

2-wires control SPI high-speed ADC -  11/10/05 EDN-Design Ideas Inverters substitute for an SPI ADC's chip-select line__ Circuit Design by Dan Meeks, Texas Instruments Inc, Austin, TX

Accessing multiple FIFOs in your FPGA Design -  For modules in the HERON-FPGA and HERON-IO families, HUNT ENGINEERING provide a comprehensive VHDL support package.  The VHDL package consists of a “top level”, with corresponding user constraints file, VHDL sources and simulation files for the Hardware Interface Layer, and User VHDL files as part of many examples.   __ Designed by Brent Knoll

Accessing SDRAM in your FPGA Design -  For modules in the HERON-FPGA and HERON-IO families, HUNT ENGINEERING provide a comprehensive VHDL support package.  The VHDL package consists of a “top level”, with corresponding user constraints file, VHDL sources and simulation files for the Hardware Interface Layer, and User VHDL files as part of many examples.   __ Designed by Brent Knoll

Add a Schmitt-trigger function to CPLDs, FPGAs & applications -  10/13/05 EDN-Design Ideas For slow-slewing signals, hysteresis solves trigger problem__ Circuit Design by Stephan Roche, Santa Rosa, CA

Add Sequencing & Shutdown Control to Regulator -  10/30/03  EDN-Design Ideas Modern microprocessor- or FP-GA-based circuits require separate and independent power-supply voltages for the core and the I/O circuits.  Some devices require stringent control of the turn-on characteristics and sequencing of these __ Circuit Design by Said Jackson, Equator Technologies Inc, Campbell, CA

Audio Project -  forXSV Board   (Univ.  of Queensland)  __

Build a UWB Pulse Generator On an FPGA -  06/23/11  EDN-Design Ideas Make pulses that reach twice an FPGA's clock frequency.  You can implement a digital UWB   (ultrawideband) pulse generator in most FPGAs.  The design lets you create a pulsed signal with a frequency that’s twice the FPGA’s clock frequency   (Figure 1).  A previous design relies on asynchronous delays to make pulses of the desired frequency.  That design, however, requires an FPGA that supports tristate pullups, such as the Xilinx Virtex 2   (Reference 1).  __ Circuit Design by Punithavathi Duraiswamy, Xiao Li, Johan Bauwelinck, and Jan Vandewege, Ghent University, IMEC/Department of Information Technology, Ghent, Belgium

Building Wireless Communications & Broadcast Systems with the HERON Range -  Wireless communications is being revolutionised by new high performance signal processing systems.  Many system building blocks can now be built using digital technology, bringing new levels of manufacturability, reliability and performance – usually at reduced cost __

Calculator -  uses8051 microcontroller and FPGA onXS40 Board to build a simple calculator __

Calculator program finds closest standard-resistor values -  31-Mar-05 EDN-Design Ideas Find the poles and zeroes of elliptic-filter designs using Darlington’s algorithm implemented on a calculator__ Circuit Design by Fernando Salazar-Martínez, Alan Altamirano-Cruz, and David Báez-López, Department of Engineering Electronics, University of the Americas, Puebla, Mexico

Calibrate scope jitter using a transmission-line loop -  09/20/01 EDN-Design Ideas Digital-clock-period jitter is the variation in the period of a clock cycle compared with a nominal  (average of many cycles] clock period.  To accurately measure period jitter using an oscilloscope, you must subtract the oscilloscope jitter from the measured jitter.  However, oscilloscopes rarely have a jitter specification, so you must determine the oscilloscope jitter__ Circuit Design by David Cuthbert, Micron Technology, Boise, ID

Circuit allows high-speed clock multiplication -  05/02/02 EDN-Design Ideas In theory, synchronous clock multiplication is an easy task.  A simple PLL with two digital dividers—one inserted just after the VCO(voltage-controlled oscillator] and the second one placed directly at the input of the phase detector—may do the job.  The flexibility of such a configuration allows for clock multiplication by any rational number__ Circuit Design by Lukasz Sliwczynski and Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow, Poland

Circuit Protects FPGAs from killer Spikes -  04/23/98 EDN-Design Ideas NOTE : File contains multiple circuits scroll to find this circuit.   A project using Xilinx FPGAs brought an interesting problem to light.  When you turn on the board, one FPGA in three succumbs to this problem.  A lot of frustration and testing uncovered a negative-going spike(Figure 1)in the 5V line from the DC/DC converter.  The system uses a DC/DC converter__ Circuit Design by  Nelson Nguyen, Anritsu Corp, Morgan Hill, CA

Circuit Provides Power Sequencing -  14-Oct-04 EDN-Design Ideas ASICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their start-up sequencing.  Often, I/O voltages, which usually have the highest voltage, must come up first, followed by all other voltage rails in a high-to-low order, with the core voltage last.  This scenario may also require that one supply rail not exceed another bythan a diode drop; otherwise, excessive c__ Circuit Design by John Betten, Texas Instruments, Dallas, TX

Circuit Sequences Supplies for FPGAs -  01/23/03 EDN-Design Ideas System designers must consider the timing and voltage differences between core and I/O power supplies(in other words, power-supply sequencing] during power-up and power-down.  The possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly.  The trigger for latch-up may occur if power supplies apply different potentials to the core and__ Circuit Design by David Daniels, Texas Instruments, Dallas, TX

CMOS Gate Implements Reverse Phase Control -  05/21/98 EDN-Design Ideas (File has seeveral  circuits, scroll down) The circuit in Figure 1 implements a "reverse" phase control, using only a single CMOS 4001 quad NOR gate.  The circuit is known as a reverse phase control because, unlike with common TRIAC or SCR controls, conduction begins at the zero crossing of the ac sine wave.  Timing of the turn-off point__ Circuit Design by JC Johnson, Lithonia Lighting, Decatur, GA

CMOS Gate Makes Long-Duration Timers using RC Components -  03/01/12  EDN-Design Ideas Use a common CMOS gate to make long duration timers using low-value RC components.  The CD4011 CMOS NAND gate has a typical input current of 10 PA at room temperature.  You can charge a capacitor connected to the gate input with currents on the order of hundreds of picoamperes and neglect the influence of the gate-input current on the charging time of the capacitor.  You normally need large-value resistors to limit currents to this low level.  These resistors are not commonly available.  You can instead use a transistor as a current attenuator, despite its more usual amplifying nature.  __ Circuit Design by Raju Baddi, Tata Institute of Fundamental Research, Pune, India

Configuring HEART, statically or dynamically -  HEART is a real time communications architecture used on HERON module carriers.  The connections are software programmable, and after they are programmed they guarantee performance.  It’s like making a phone call, first you establish the connection and then you can use that connection when you want.  If your system does not send data, the connection remains there with the bandwidth available for your use.   __ Designed by Brent Knoll

Connecting the PowerPC Processor to Hardware -  Xilinx Virtex-II Pro FPGAs provide one or more embedded PowerPC processor cores along with the usual array of Virtex-II FPGA technology including logic slices, dedicated multipliers and Block RAM.  Combining a PPC processor core with the Virtex-II FPGA fabric brings a huge amount of flexibility – the possible uses are numerous.  However an interesting design challenge is created.  How can the processor and FPGA be used together in a way that makes the best use of the power of each element?  __ Designed by Brent Knoll

Control an FPGA bus without using the processor -  EDN-Design Ideas 04/27/2016    A bit of added hardware lets FPGA engineers access peripherals without having to deal with the processor__ Circuit Design by Noe Quintero

Converting your FPGA Design from Hardware Interface Layer V1.x to V2.x -  For modules in the HERON-FPGA and HERON-IO families, HUNT ENGINEERING provide a comprehensive VHDL support package.  The VHDL package consists of a “top level”, with corresponding user constraints file, VHDL sources and simulation files for the Hardware Interface Layer, and User VHDL files as part of many examples __ Designed by Brent Knoll

CPLD automatically powers itself off -  04/13/06  EDN-Design Ideas Add a few discrete components to a CPLD to implement a battery-powered system's power-down circuit__ Circuit Design by Rafael Camarota, Altera Corp, San Jose, CA

CPLD autonomously powers battery-powered systE - M -  12-Apr-07 EDN-Design Ideas CPLD controls power-on and off of intermittent-battery-powered system__ Circuit Design by Rafael Camarota, Altera Corp, San Jose, CA

CPLD Interface Files -  for the XSV Board projects (Univ.  of Queensland)   __

CPLD’s internal oscillator performs autocalibration -  09/13/07  EDN-Design Ideas An autocalibration sequence synchronizes a CPLD's internal oscillator with an external crystal oscillator, enabling ±0.3% accuracy__ Circuit Design by Rafael Camarota, Altera Corp, San Jose, CA

Data Transfers to a Host PC or a processor based Module -  The HERON and HEART product range is designed for use in real time systems.  HUNT ENGINEERING provides the hardware and the tools you need to be able to develop your application with them.   __ Designed by Brent Knoll

Data Unpacking Techniques for C6000 Systems -  In real C6000 systems such as those being built with HERON modules, it is necessary to connect the processors to “real world” data via devices like A/Ds and D/As.  The processing power of the C6000 makes it sensible to process multiple channels of data per processor, which leads to a need for multi-channel I/O devices such as the HEGD9 and HEGD11 A/D modules.  The data from the channels is then interleaved into a single communication stream – which brings additional challenges to the processor.  This paper looks at various ways that the C6000 can deal with this data __ Designed by Brent Knoll

DDC with FPGA (using HERON-IO2V) -  The advent of larger and faster Xilinx FPGA’s has opened up the field of digital signal processing.  The large array of configurable logic blocks within the FPGA give great flexibility together with speed, once configured the FPGA is not as flexible as a processor but is much faster.  For many DSP applications speed is important especially for the initial processing of the data, after which the data rate reduces and becomes more manageable. __ Designed by Brent Knoll

DDS with HERON FPGA -  The HERON-FPGA family is ideal for many of the building blocks of digital communications.  Providing large easily-programmed gate arrays, often combined with interface elements like ADC or DACs, they can be used to implement many system components. __ Designed by Brent Knoll

Debug a Microcontroller-To-FPGA Interface From the FPGA Side -  12/05/09 EDN-Design Ideas Monitor activity through a JTAG download cable__ Circuit Design by Bibo Yang, Sunrise Telecom, Beijing, China

Developing a real time system-an example -  The system will be dealing with data that comes from the real world.  To begin with we will replace that data with a simple count so that we can check it’s correctness as it passes through the system.  I chose to use an external clock to generate the data samples.  Then I could easily change the data rate each time I wanted to establish the limit of performance of the system __

Digital Down Conversion theory -  The advent of larger and faster Xilinx FPGA’s has opened up the field of digital signal processing.  The large
array of configurable logic blocks within the FPGA give great flexibility together with speed, once configured the FPGA is not as flexible as a processor but is much faster.  For many DSP applications speed is important especially for the initial processing of the data, after which the data rate reduces and becomes more manageable.   __ Designed by Brent Knoll

Dual Output Supply Powers FPGAS from 3.3V & 5V Inputs -  DN311 Design Notes___ Linear Technology/Analog Devices

External Memory Types for 'C6000 Systems The C6000 processor core can place intense demands on its memory subsystem.  In any one cycle, up to eight instruction
words can be fetched; in addition, two data words can be requested, while the DMA can perform a further access.  With a
potential maximum of eleven 32-bit accesses being performed every cycle, the chip's designers have spent considerable effort
tuning the on-chip memory system for best performance. __ Designed by Brent Knoll


Gate Arrays:  #'s - E       F - Q        R - Z

 


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