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Gate Array Circuits
Gate Arrays:  #'s - E       F - Q        R - Z

Last Updated: December 31, 2017 06:49 AM

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RISC P implements fast FIR filter -  01/21/99 EDN-Design Ideas NOTE : contains several designs, scroll to find this one.  When it comes to implementing a fast FIR filter, current RISC Ps can compete with DSP Ps.  The FIR algorithm continuously implements the following equation: N=n1 Out=Sum[in(t[-]n)coeff(n)] N=0, where N is the number of taps, or the number of multiply-accumulate (MAC) instructions of the filter.  Using a delay line to implement this equation is common and involves the ability to manage a circular buffer.  __ Circuit Design by Sorin Zarnescu, NEC Electronics, Santa Clara, CA

RISC P Supports IEEE Parallel-Port Standard -  01/18/96 EDN-Design Ideas Figure 1 shows the logic required to implement an IEEE-1284-compliant parallel port, using the Am29202 RISC processor.  The IEEE-1284 spec allows for multiple modes of operation.  The first is the compatibility mode, which designates the parallel port of the original IBM PCs.  This mode has a peak download capability of 220 kbytes/sec.   __ Circuit Design by Ronald Stence, Advanced Micro Devices, Austin, TX

Sampling of Signals for Digital Filtering & Gated Measurements -  DN2 Design Notes___ Linear Technology/Analog Devices

Scheme Adds Sequencing & Shutdown Control to Regulator -  10/30/03  EDN-Design Ideas Modern microprocessor- or FP-GA-based circuits require separate and independent power-supply voltages for the core and the I/O circuits.  Some devices require stringent control of the turn-on characteristics and sequencing of these __ Circuit Design by Said Jackson, Equator Technologies Inc, Campbell, CA

SDRAM interface slashes pin count -  03/29/01 EDN-Design Ideas Many designs need deep buffering but don't require ultrahigh-memory bandwidth.  Examples include image and audio processing, as well as some deep-FIFO applications.  These designs often use a singlex8 SDRAM device that connects to an FPGA or ASIC.  This approach solves the buffering problem but also burns a lot of valuable pins, which can be as many as 27 for a single SDRAM device__ Circuit Design by Tim Hellman

Sequence Supplies for FPGAS -  01/23/03 EDN-Design Ideas System designers must consider the timing and voltage differences between core and I/O power supplies(in other words, power-supply sequencing] during power-up and power-down.  The possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly.  The trigger for latch-up may occur if power supplies apply different potentials to the core and__ Circuit Design by David Daniels, Texas Instruments, Dallas, TX

Simple Circuit FIFO provides data-width conversion -  09/26/02  EDN-Design Ideas Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements.  However, in some applications, you need FIFO buffers for data conversion.  One example is the case in __ Circuit Design by David Lou, Ghent University, Ghent, Belgium

Simple Circuit provides power sequencing -  14-Oct-04 EDN-Design Ideas ASICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their start-up sequencing.  Often, I/O voltages, which usually have the highest voltage, must come up first, followed by all other voltage rails in a high-to-low order, with the core voltage last.  This scenario may also require that one supply rail not exceed another bythan a diode drop; otherwise, excessive c__ Circuit Design by John Betten, Texas Instruments, Dallas, TX

Single-MOSFETs gate & Modulate -  EDN-Design Ideas 07/27/2015    The humble discrete MOSFET shows its versatility in This design idea     __ Circuit Design by Umar Shami

Speed FPGA Debug with Mixed-Signal Oscilloscopes -  Application Note___ Aligent

SRAM Interface -  for the XSV Board (Univ.  of Queensland)  __

Swapping bits improves performance of FPGA PWM counter -  09/13/07  EDN-Design Ideas A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC__ Circuit Design by Stefaan Vanheesbeke, Ledegem, Belgium

Tool generates HDLs directly from Simulink -  09/19/06 EDN-Design Ideas The folks trying to model multiple DSP functions to implement in FPGAs or ASICs using MathWorks tools will be happy to learn that the company's latest release, Simulink HDL Coder, automatically generates cycle-accurate, bit-accurate Verilog or VHDL directly from Simulink__ Circuit Design by Michael Santarini, Senior Editor -- EDN

Two Gates Expand ASICs Memory Decoding Range -  03/29/01 EDN-Design Ideas Many electronic circuits implement chip-select lines on an ASIC.  From  beginning of  design cycle,  chip selects, CS0 to CS4, have defined bases on  memory map  (Figure 1).  Adding functions__ Circuit Design by Vinh Hoang, Ericsson Inc, Brea, CA

Two wires control SPI high-speed ADC -  11/10/05 EDN-Design Ideas Inverters substitute for an SPI ADC's chip-select line__ Circuit Design by Dan Meeks, Texas Instruments Inc, Austin, TX

USB Macro -  that combines a complete USB transaction layer with an 8051 microcontroller core and a functional block that implements the application-specific functions.  This macro was developed and is supported by Trenz Electronics for use with an XSV Board __

Using the 16700 Logic Analyzer with the Xilinx ChipScope ILA -  Application Note___ Aligent

VG Out -  for the XSV Board (Univ.  of Queensland)  __

VHDL IP Stack -  for the XSV Board (Univ.  of Queensland)  __

Video In -  for the XSV Board (Univ.  of Queensland)  __

Virtex 5 Adds PCI Express & 10 Gbit Ethernet cores -  10/18/06 EDN-Design Ideas Xilinx has released the second platform derivative of its Virtex-5 FGPA family targeting markets requiring serial connectivity __ Circuit Design by Michael Santarini, Senior Editor -- EDN

Walking Bit -  shifts a1 through a register mapped to the 7-segment LED.  This design shows the interactions between the XC4000 FPGA and the 8031 microcontroller on the XS40 Board __

Gate Arrays:  #'s - E       F - Q        R - Z

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