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Gate Array Circuits
Gate Arrays:  #'s - E       F - Q        R - Z

Last Updated: December 31, 2017 06:49 AM

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Fast Integer Multipliers Fit In FPGA -  05/12/94 EDN-Design Ideas You can fit a fast and compact digital multiplier into a field-programmable gate array(FPGA].  The technique involves using small look-up tables to find partial products and then adding the partial products.  The key factor for making the design compact, fast, and easy to implement is to make the look-up tables for the partial products as small as possible.  This multiplier can quickly multiply a number by a constant; changing the constant momentarily takes the multiplier off-line__ Circuit Design by Kenneth David Chapman, Xilinx Ltd, byfleet, Surrey, UK

Fast, low-noise JFET Amp is stable over temperature -  EDN-Design Ideas 08/03/2015    This Design Idea combines the strong points of JFETs and CFAs to make a high-impedance amplifier thats fast, stable over temperature, and quiet__ Circuit Design by Shyam Sunder Tiwari

FIFO Makes Cheap Waveform Generator -  12/21/95 EDN-Design Ideas The circuit in Figure 1 shows the basic configuration of a simple and inexpensive arbitrary waveform generator.  IC1s 82C54 produces the timebase for the wave table.  This IC can generate a 152-Hz to 5-MHz clock under software co__ Circuit Design by Todd Williams, Napco Security Systems Amityville, NY

FIFO provides data-width conversion -  09/26/02  EDN-Design Ideas Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements.  However, in some applications, you need FIFO buffers for data conversion.  One example is the case in __ Circuit Design by David Lou, Ghent University, Ghent, Belgium

Filters with HERON FPGA -  The HERON-FPGA family is ideal for many of the building blocks of digital signal processing (DSP) more typically implemented in DSP processors.  They have a high gate count, often combined with peripherals such as high-speed ADC or DAC converters.  In signal processing systems, the FPGA can be used to implement functions like up-sampling (interpolation) or pulse shaping before transmission, or Digital Down Conversion (DDC) for a receive chain.  Many other functions can also be implemented __ Designed by Brent Knoll

FPGA Configures Simple Circuit BCD Adder -  02/15/96 EDN-Design Ideas Often, the easiest way to execute a calculation with BCD operands is to convert the BCD inputs to binary numbers, do the calculation in normal binary fashion, then convert the binary result back to BCD notation.  However, for some calculations, such as addition, it can be easier and more efficient to add the BCD numbers directly, without using binary conversions.  The block diagram in Figure 1 shows how to implement a BCD adder in an FPGA.__ Circuit Design by Chris Jones, Cypress Semiconductor San Jose, CA

FPGA Emulates 74X74 Flip-Flop -  10/12/95 EDN-Design Ideas The Xilinx 4000 Series FPGA library contains a D-type flip-flop with either asynchronous preset or clear, but not both.  The circuit in Fig 1 provIdeas both functions, thereby eliminating the need to use discrete 74X74 ICs.  The circuit consists of a set flip-flops, two reset flip-flops, a 4:1 multiplexer(of which you use only two channels], and a few logic gates.  If either PR__ Circuit Design by Keith Gomarac, AIL Systems, Lancaster, CA

FPGA implements X.50 Division 3 recommendation -  04/13/00 EDN-Design Ideas The scheme in Figure 1a uses five delay cells and an XOR gate to configure the data stream for the X.50 Division 3 recommendation of ITU-T.  The X.50 recommendation defines the fundamental parameters of a multiplexing scheme for interworking data__ Circuit Design by Andres Martinez, Alcatel, Ramirez de Prado, Spain

FPGA makes Simple Circuit FIFO -  26-Oct-00 EDN-Design Ideas The circuit in Figure 1 is an FPGA-based, synchronous FIFO that uses the same clock for read and write operations.  The circuit can generate FIFO-occupancy flags with a minimum of logic.  The boxed area in Figure 1 shows a more conventional occupancy meter.  The circuit is implemented in a demultiplexer that writes data in the FIFO when the data arrives and reads data according to FIFO occupancyPDF contains several circuits, scroll to find this one__ Circuit Design by Design by Luis Miguel Brugolaras, SIRE, Madrid, Spain

FPGA Memory Controller Links Embedded P to Cache-Enhanced DRA -  01/19/95 EDN-Design Ideas DRAM chips often lack the performance that embedded systems require.  Also, SRAM takes up too much space and is too expensive for any application using over 1 Mbyte of memory.  But designers have another option: a memory built with DRAM enhanced with an on-__ Circuit Design by James Joseph and Charles Brown, Ramtron International Corp, Intel Corp

FPGA or DSP -  The DSP is a specialised microprocessortypically programmed in C, perhaps with assembly code for performance.  It is well suited to extremely complex maths-intensive tasks, with conditional processing.  It is limited in performance by the clock rate, and the number of useful operations it can do per clock.  As an example, a TMS320C6201 has two multipliers and a 200MHz clock so can achieve 400M multiplies per second.   __ Designed by Brent Knoll

FPGA Transfers Data On Every Clock Cycle -  03/03/94 EDN-Design Ideas The circuit in Fig 1  uses the Actel 1240's latches in a static-RAM(SRAM) interface.  This interface transfers data on every clock cycle using a minimum of logic.   (The counter macro in the figure exists solely to provide sequential addresses.)__ Circuit Design by Gary Peyrot,  Three Step Development, West Hills, CA

FPGA-configuration scheme is flexible -  22-Jan-04 EDN-Design Ideas FPGAs are popular in circuit design because of their flexibility and efficiency.  You need to program an FPGA by loading configuration data into designated configuration memory.  Because most FPGAs have no internal nonvolatile memory, you must store the configuration files in external devices.  When you use many FPGAs in a design, it is inadvisable to put a large amount of external memories near t__ Circuit Design by Zhe Lou, Ghent University, Ghent, Belgium

FPGA's Tri-State Buffers Build 32x32 CroSSBar -  12/08/94 EDN-Design Ideas The ramp generator in Fig 1a and the triangle-wave generator in Fig 1b charge capacitor C1 linearly.  The key to the circuits' linearity is an op-amp adder that sums a reference voltage with the voltage on C1.  For Fig 1a's ramp generator, the adder comprises op-amp IC1, R4, R5, and associated components__ Circuit Design by Bernie New, Xilinx Inc, San Jose, CA

Gate Deep Oscillator -  This is just a variable oscillator based on a bf245 or k 161 fet.  By changing the coil it can generate frequency between 0.5 and 300 MHZ.  this circuit is useful to test radio circuit such as filter, receiver, transmitter and so on.   __ Designed by Alfred73

Gated oscillator holds last level -  EDN-Design Ideas 09/22/2014     Unlike a typical gated oscillator, this one holds its current output level when turned off__ Circuit Design by Einar Abell

Introduction to XS Volt Board Designs -  done by the University of Queensland __

JBITS XHWIF Interface -  for the XS40-005XL Board __

JBITS XHWIF Interface #2 -  for the XSV-100 Board __

Look-Ahead Approach Tames Large FPGA Counter -  12/22/94 EDN-Design Ideas The T flip-flops and look-ahead technique in Fig 1 allow you to program large, fast counters in FPGAs (field-programmable gate arrays).  The look-ahead technique detects when the least-significant 4-bit block (Q3 through Q0) has the value 1110.  The technique registers this event in a D flip-flop to create the look-ahead signal (LA0 through LA4).__ Circuit Design by Jay Legenhausen, Cypress Semiconductor, San Jose, CA

Macro -  that combines a complete USB transaction layer with an 8051 microcontroller core and a functional block that implements the application-specific functions.  This macro was developed and is supported by Trenz Electronics for use with an XSV Board __

Measuring Jitter in Digital Systems an 1448-1 -  Application Note___ Aligent

Midrange Device includes SERDES function -  09/19/06 EDN-Design Ideas Lattice Semiconductor has announced a midcapacity, midpriced FPGA that includes some of the high-speed, high-end functions you typically only find in the most advanced and priciest Xilinx Virtex and Altera Stratix FPGAs.  __ Circuit Design   Michael Santarini, Senior Editor

Modulator's Design Cuts FPGA's Gate Count -  01/06/94 EDN-Design Ideas The pulse-width modulator(PWM]macro in Fig 1 requires only half as much logic as a conventional 2-counter design.  With the help of extra logic, a synchronous, loadable up/down counter can encode information in the duty cycle of a constant-frequency, constant-amplitude signal__ Circuit Design by Bernie New, Xilinx, San Jose, CA

PC to SRAM Interface -  for the XSV Board (Univ.  of Queensland)  __

PC/XS Transfer -  A circuit and C code for bidirectional transfer of data between an XS40 Board and a PC __

PC's parallel port & a PLD host multiple stepper Motors & switches -  02/16/06 EDN-Design Ideas Well-suited for robotics applications requiring motion in several direction ____ Circuit Design by Eduardo Perez-Lobato

Priority Encoders Slip Into FPGA -  02/17/94  EDN-Design Ideas The standard 8-to-3 priority encoder's design, in maximal canonical form (such as the 74148), suffers from drawbacks when you try to use the design as a macro in a large digital project.  The drawbacks are:  The number of inputs to the gates varies from two to nine; If any of the inputs develops a stuck-at-zero or stuck-at-one fault, such a fault is difficult to detect; and Reconfiguring the design to suit a fault-tolerant design is difficult.  __ Circuit Design by Swapnajit Mittra, Baharat Electronics, Bangalore, India

Protects FPGAS from Killer Spikes -  04/23/98 EDN-Design Ideas A project using Xilinx FPGAs brought an interesting problem to light.  When you turn on the board, one FPGA in three succumbs to this problem.  A lot of frustration and testing uncovered a negative-going spike (Figure 1) in the 5V li__ Circuit Design by Nelson Nguyen, Anritsu Corp, Morgan Hill, CA

Provides Power Sequencing -  14-Oct-04 EDN-Design Ideas ASICs, FPGAs, and DSPs can require multiple supply voltages with restrictions on their start-up sequencing.  Often, I/O voltages, which usually have the highest voltage, must come up first, followed by all other voltage rails in a high-to-low order, with the core voltage last.  This scenario may also require that one supply rail not exceed another bythan a diode drop; otherwise, excessive c__ Circuit Design by John Betten, Texas Instruments, Dallas, TX

PS/2 Interface -  for the XSV Board (Univ.  of Queensland)  __

Gate Arrays:  #'s - E       F - Q        R - Z

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