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Integrated scan techniques ease chip & board tests - 11/21/96
EDN-Design Feature. Building Today's designers, in an effort to meet the
demands of increasing chip densities and quality requirements, are employing
automatic test-pattern generation, augmented by scan techniques, to achieve
high, predictable fault coverage and minimize test times....[Design Feature by
Sanjay Patel and Ian Burgess, Mentor Graphics Silicon Systems DFvision]
Interfacing 5 Volt CMOS to 12 Volt loads - The circuit above is
designed to be used with the bi-directional lamp sequencer shown above on this
same page. Two additional transistors are used to increase the current from the
74HCT138 decoder to control 12 volt 25 watt lamps. A 6.8 volt/1 watt zener diode
is used in series with the ground connection of all the CMOS ICs (74HC14, CD4516
and 74HC138s) so that the total voltage across the CMOS devices will be about
5.2 volts and the outputs will move from +12 to about +7 when selected. The
2N2905/PNP transistor stage is connected as an emitter follower which provides a
high impedance to the....[Bill Bowden's circuit]
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